The present application relates in general to electronic device structures, and more particularly, to transistor structures for semiconductor integrated circuit devices.
Patterns of MOS transistors in an integrated circuit device may need to be formed to have accurate sizes/dimensions so that the MOS transistors may provide desired operational characteristics. Due to the high integration of semiconductor devices, however, MOS transistors having a designed layout may be difficult to form on a substrate, even though correction (e.g., optical proximity correction OPC, process proximity correction PPC, etc.) may be performed for photolithography operations.